AMD says its 6th Gen EPYC 9006 “Venice” server processors are in production. A new AMD white paper goes further, claiming performance leads over Nvidia’s Vera and Intel’s Xeon 6980P, including 2.24 times the throughput of a two-socket Vera system for its flagship 256-core EPYC 9996.
What AMD has not said is when servers built on the chips will ship, and every performance figure in the paper is AMD-reported, with the Vera comparisons relying on Nvidia’s own estimates. For anyone planning AI infrastructure, the distance between “in production” and “available,” and between “AMD says” and “independently measured,” is the real story.
Table of Contents
What AMD announced
On 18 September, AMD published a newsroom post saying Venice is “in production today.” The company added that major OEM platforms (servers from system makers) are on schedule to launch, and that leading cloud providers will begin deploying the chips later this year.
The post accompanies a white paper, AMD EPYC Server CPU Architecture and Performance Overview, which sets out AMD’s benchmark results. The production news itself is not new: AMD announced a production ramp in May and formally introduced the EPYC 9006 family in July. The September post is a company blog, not a fresh launch.
AMD’s argument is that AI agents don’t run only on GPUs. A single request can trigger data retrieval, tool calls and code execution, much of it handled by server CPUs. AMD says different CPUs suit different stages of that work.
Where Venice stands: from production ramp to availability
A chip in production is being manufactured. That does not mean servers can be ordered or cloud instances opened to customers.
AMD’s own materials give no ship date. Phoronix, which attended AMD’s launch briefings, reported that the top-end SP7 line would not be available until the fourth quarter of 2026. It also noted that AMD shared no SKU tables (the list of individual chip models), which led some observers to view July’s event as a soft launch.
| Date | Milestone | Source and status |
|---|---|---|
| 21 May 2026 | AMD announces a Venice production ramp on TSMC’s 2nm process in Taiwan | AMD press release; company statement |
| 22–23 Jul 2026 | EPYC 9006 formally announced at Advancing AI; four product lines outlined | AMD; Phoronix |
| 23 Jul 2026 | Server makers issue statements; none gives a ship date | AMD partner quotes |
| 18 Sep 2026 | AMD publishes blog post and performance white paper | AMD |
| Q4 2026 | SP7 availability expected | Press-reported (Phoronix); not stated in AMD documents |
| 2027 | Venice-X expected; LP line follows in the second half | Press-reported (Phoronix) |
The EPYC 9006 family and what’s new
AMD describes four lines, each aimed at a different job.
| Line | Aimed at (per AMD) | Cores | Timing |
|---|---|---|---|
| SP7 | Dense agent workloads; high-frequency versions as GPU host chips | Up to 256 cores, 512 threads | Q4 2026 (press-reported) |
| SP8 | Enterprise, edge and power-constrained racks | 8 to 128 cores | Not stated by AMD |
| 9006X SP7 | Scientific and cache-heavy work; three times the L3 cache per core of SP7 | Not specified by AMD in the announcement | 2027 (press-reported) |
| LP (formerly “Verano”) | AI host-node chip using LPDDR memory | Not specified | Second half of 2027 (press-reported) |
Venice is built on AMD’s Zen 6 and Zen 6c core designs. Compared with AMD’s previous generation, the changes are largely about feeding more cores with more data. AMD says the top parts move from 192 to 256 cores and from 12 to 16 memory channels. They also support a faster memory-module type called MRDIMM, at up to 12,800 megatransfers per second.
AMD puts theoretical peak memory bandwidth at about 1.6 terabytes per second per processor, against 614 gigabytes per second before. The chips also add PCIe Gen 6, which AMD says doubles per-lane bandwidth, and CXL 3.1, a standard for memory expansion. The “512 threads” figure reflects simultaneous multithreading, where each core runs two threads.
AMD now quotes “Default CPU Power” instead of the older TDP rating. In its benchmark footnotes, the 9996 runs at 600 watts. Phoronix reported that AMD shared no SKU tables at its launch briefings, and we found no published pricing.
What the benchmarks show, and how AMD ran them
AMD’s per-core and platform comparisons with Vera come from SPECrate 2026 Integer, an industry test that measures how much work a processor completes when running many program copies at once. AMD describes its results, and Nvidia’s, as estimates. Its stated reason is that SPEC rules bar publishing official results for hardware that isn’t publicly available yet.
Per-core performance versus Nvidia Vera
AMD says Venice delivers 1.2 times the per-core performance of Nvidia’s 88-core Vera. The newsroom post attributes this to the EPYC 9996, but AMD’s footnotes show the test used a 96-core configuration cut down from the 256-core chip. The scores are estimates: 1,210 for a two-socket AMD system (6.3 per core) against 925 for a two-socket Vera system (5.3 per core). AMD took Vera’s score from Nvidia’s own white paper.
Platform-level performance versus Vera
AMD’s 2.24x figure compares 2,070 for a two-socket EPYC 9996 system against the same 925 for Vera. But that is 512 AMD cores against 176 Vera cores, so it is a measure of total throughput, not efficiency per core.
By our own arithmetic on AMD’s numbers, 2,070 divided by 512 cores is about 4.0 per core, against Vera’s 5.3. That suggests the 1.2x per-core result describes the 96-core configuration, not the full 256-core part.
Enterprise and cloud-native workloads versus Intel
AMD reports gains of 2.4x to 3.7x over Intel’s Xeon 6980P: 2.4x on Java, 2.5x on OpenSSL, 2.6x on a MySQL transaction test, 2.9x on Redis, 3.5x on MongoDB and 3.7x on NGINX. The 3.7x is a single workload, and Vera was not tested in this group.
These are one-socket comparisons of a 256-core AMD chip against a 128-core Intel chip. Dividing NGINX’s 3.7x by the 2x core-count advantage gives roughly 1.8x per core (our calculation). AMD ran these tests itself, on its own reference platform for its chips. Some results also include an AWS Graviton5 instance rented from Amazon’s cloud.
The rack-level model
AMD estimates about 3.4 times Vera’s throughput in a modeled 100-kilowatt rack. This is a model, not a measurement. Vera’s baseline was scaled up from Nvidia’s earlier Grace chip using third-party data, and AMD’s own methodology paper calls the outputs directional. AMD’s earlier document and the body of its white paper give 3.3x rather than 3.4x.
| AMD’s claim | What was measured | Key condition |
|---|---|---|
| 1.2x per-core vs. Vera | Estimated SPECrate 2026 Integer, two sockets, 96 cores enabled | Vera score from Nvidia’s white paper; unaudited |
| 2.24x platform vs. Vera | Same test, full two-socket systems | 512 cores vs. 176 |
| 2.4x–3.7x vs. Xeon 6980P | Java, OpenSSL, MySQL, Redis, MongoDB, NGINX | One socket; 256 vs. 128 cores; AMD-run; Vera not tested |
| About 3.4x rack vs. Vera | Modeled 100 kW rack | Estimate with scaled Vera baseline; 3.3x in earlier AMD documents |
Why the comparisons need context
Several configuration details complicate direct comparisons.
Compilers. A compiler turns source code into the program that runs. Tom’s Hardware reported that AMD used a newer version (GCC 16.1) than the one behind Nvidia’s Vera numbers (GCC 15.2). AMD’s own footnotes are inconsistent: one lists GCC 15.2 for both sides, while others list 16.1 for the same 1,210 score.
Core configuration. AMD’s footnotes give the 96-core chip a 600-watt budget in its memory-bandwidth test and state no power figure for the SPEC estimates. Tom’s Hardware reported that the earlier SPEC numbers also used 600 watts and that AMD’s 96-core high-frequency model tops out at 500 watts. We have not independently confirmed those two points.
The Vera baseline. Vera’s SPEC scores are Nvidia’s own estimates from a reference system that, per independent analysis by Chips and Cheese, was not generally available. AMD’s memory-bandwidth comparison, roughly 18% higher overall and 8% per core, uses a Vera figure from a Phoronix review that ran under Nvidia-controlled conditions. AMD measured its own chip separately.
Power. AMD’s July blog uses the 256-core chip at 400 watts for its agents-per-watt claim, while the September benchmarks run it at 600 watts. Efficiency comparisons need matched power figures, and AMD has not published enough detail here to calculate them.
None of this shows the results are wrong. It means the numbers are conditional. Tom’s Hardware also observed that peak benchmark performance is only one factor in server purchasing.
Separately, Phoronix noted that Intel’s next server generation, Diamond Rapids, is not expected until at least 2027.
Who is building Venice systems
On the server-maker side, statements are plentiful and dates are absent.
| Company | System named | Ship date stated |
|---|---|---|
| Supermicro | H15 server portfolio | None |
| Lenovo | ThinkSystem SC755 | None |
| Dell | “Latest generation” PowerEdge; no model named | None |
| HPE | ProLiant; no model named | None |
ASUS, Giga Computing, ASRock Rack, MiTAC, MSI, Pegatron and QCT also issued statements through AMD. None of the statements gives a ship date.
On the cloud side, AMD says leading providers begin deploying later this year but doesn’t name them. Oracle Cloud Infrastructure said it is extending its collaboration with AMD through “future” Venice CPUs. We found no other cloud provider’s commitment in AMD’s materials.
What it means for AI infrastructure planning
Verified facts support several decision points, not a buy-or-wait recommendation.
- Timing. Phoronix reports SP7 availability in the fourth quarter, with the Venice-X and LP lines expected in 2027. SP8 timing was not stated in AMD’s announcement materials.
- Which chip a claim describes. The Vera per-core claim covers a 96-core configuration. Throughput and rack claims apply to the 256-core chip.
- Platform demands. AMD’s fastest memory test used 16 MRDIMM modules per processor, and its benchmark chip runs at 600 watts.
- Licensing and memory costs. AMD notes that enterprise software is often licensed per core, which makes per-core comparisons matter. It also says memory can be a large share of server cost in mid-2026.
Benchmarks are not deployments, and none of these figures describes how Venice performs in a particular data center.
What we still don’t know
- When individual server platforms will ship.
- Which cloud providers will deploy Venice this year.
- Pricing and the full list of chip models: we found neither published.
- How independent testing compares with AMD’s figures.
- Details such as how many benchmark copies were run and how much power the systems drew.
Not finding something is not proof it doesn’t exist. These are gaps in what is public.
Latest developments
As of 21 September 2026, coverage of the white paper has focused on its methodology, including the Tom’s Hardware analysis cited above. We found no new AMD availability announcement and no independent Venice benchmarks. Phoronix has said it plans to publish testing without restrictions.
Bottom line
The evidence supports a narrow conclusion. AMD says Venice is in production and has named partners, but availability is unconfirmed and performance figures are AMD-reported, tied to specific configurations. The Vera comparison in particular rests on estimates from both sides.
To watch next: independent benchmarks, per-vendor ship dates, a published chip list with pricing, named cloud deployments, and official SPEC results once hardware is publicly available.
FAQ
Is AMD EPYC Venice in production? AMD says yes. It announced a production ramp on 21 May and said on 18 September that Venice is in production. We found no independent confirmation of volumes, and Venice is not yet generally available.
When will EPYC Venice servers be available? AMD’s materials give no dates. Phoronix reports SP7 availability in the fourth quarter of 2026 and Venice-X in 2027, with the LP line in the second half of 2027. AMD says cloud providers begin deploying later this year.
Which OEMs are building EPYC 9006 servers? Supermicro, Lenovo, Dell, HPE, ASUS, Giga Computing, ASRock Rack, MiTAC, MSI, Pegatron and QCT have all made statements. Supermicro and Lenovo name specific systems. None gives a ship date.
How does the EPYC 9996 compare with Nvidia Vera? AMD estimates 1.2x per-core performance, but for a 96-core configuration, and 2.24x platform-level performance, with 512 cores against 176. Both are unaudited estimates using Nvidia’s own Vera figures, and the compiler versions are stated inconsistently.
What are the EPYC 9996’s key specifications? AMD lists 256 cores and 512 threads, 16 DDR5 memory channels, MRDIMM support up to 12,800 MT/s, about 1.6 TB/s theoretical peak bandwidth, PCIe Gen 6 and CXL 3.1. Its benchmark configuration ran at 600 watts. We found no full SKU table or pricing published.
Have independent EPYC Venice benchmarks been published? Not as of 21 September that we could find. Tom’s Hardware has analyzed AMD’s methodology but did not test the chips, and Phoronix says testing is planned.
What does Venice mean for agentic AI infrastructure? AMD’s argument is that agent workloads such as tool calls, retrieval and code execution rely heavily on CPUs. Its Venice family targets that work. The supporting performance data is AMD-reported, and independent, real-world evidence is still pending.